With the progress in semiconductor processes, it has become possible to mount plural DACs in the same semiconductor integrated circuit. In a test for such semiconductor integrated circuit having plural DACs, there is a tendency that the test time is increased as the number of the DACs mounted becomes larger or the resolution (resolution capability) thereof becomes higher.
Conventionally, as one of approaches to reduce the test time for the semiconductor integrated circuit of this type, there is a method of testing the outputs of the DACs using analog-to-digital converters (hereinafter referred to as ADCS). However, since the ADCs which are higher in precision than the DACs are required in the test for the high-resolution DACs, the circuit scale of the semiconductor integrated circuit having these DACs and ADCs is undesirably increased.
Besides, as disclosed in Patent Document 1 or Patent Document 2 which is a laid-open unexamined publication of Patent Document 1, there is a method of comparing three or more DACs using a comparator, and performing a judgment on the basis of the comparison result.
Patent Document 1: Japanese Published Examined Application No. Sho. 64-9771
Patent Document 2: Japanese Published Unexamined Application No. Sho. 61-16624